An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, capacitors, and resistors. Commonly known as a “chip” or a “package”, an integrated circuit is generally encased in hard plastic. The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement.
Circuit designers use a variety of software tools to design electronic circuits of an IC. The software tools used for designing an IC produce, manipulate, or otherwise work with the circuit layout at very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including millions of such components interconnected to form an intended electronic circuitry. An interconnected group of components is called a net.
An IC may use many layers of silicon to implement a circuit. In other words, components forming the circuit may be placed on different layers of silicon in a chip. Interconnects connecting the components on one layer to components on different layers go through the silicon layer. Such interconnects are also known as Through Silicon Vias (TSVs, or via).
The software tools manipulate these components at the components level, or blocks of components level. A block of components is also known as a global cell or g-cell. A g-cell in an IC design is a portion of the IC design. One way of identifying g-cells in an IC design is to overlay a grid of imaginary vertical and horizontal lines on the design, and deeming each portion of the IC design bound by horizontal and vertical lines as a g-cell. The horizontal or vertical lines bounding a g-cell are called cut-lines.
Imposing such a grid on an IC design abstracts the global routing problem away from the actual wire implementation and gives a more mathematical representation of the task. A net may span one or more g-cells and may cross several cut lines.
An IC design software tool can, among other functions, manipulate cells, or interconnect components of one cell with components of other cells, such as to form nets. Such a cell is distinct from the g-cell in that this cell is a logic component, such as a semiconductor gate. The interconnects between components are called wires. A wire is a connection between parts of electronic components, and is formed using a metallic material that conducts electricity.
Placement problem is the problem of placing the cells of a chip such that the design meets all the design parameters of the chip. Routing is the process of connecting the pins after placement. In other words, placement results in a rendering of the components of various cells as being located in certain positions in the design, whereas routing results in a rendering of how the metal layers would be populated with that placement.
A wire can be designed to take any one of the several available paths in a design. Placement of a wire on a certain path, or track, is a part of routing.
A layer is typically designated to accommodate wires of a certain width (wire code). Generally, the wider the wire width of a layer, the faster the net routed on that layer. Faster layers, to with, layers with larger wire widths, can accommodate fewer components or nets as compared to slower layers with narrower wire widths.
A router is a component of an IC design tool that performs the routing function. Once the placement component—known as a placer—has performed the placement function, the router attempts to connect the wires without causing congestion. For example, if a design parameter calls for no more than five wires in a given area, the router attempts to honor that restriction in configuring the wiring. Such limitations on the wiring are a type of design constraints and are called congestion constraints.
A global router divides the routing region into small tiles (g-cells) and attempts to route nets through the g-cells such that no g-cell overflows its capacity. Global routing, or rough routing, is the process of connecting a g-cell to other g-cells.
After global routing, wires must be assigned to actual tracks within each tile, followed by detailed routing, which must connect each global route to the actual pin shape on the cell. Another type of router—known as the detailed router—performs the detailed routing. The global and detailed routing produced during the design process is collectively referred to as “routing” and is usually further modified during optimization of the design.